/***************************************************************************//**
* \file cyhal_triggers_explorer.h
*
* \brief
* Explorer family HAL triggers header
*
********************************************************************************
* \copyright
* (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYHAL_TRIGGERS_EXPLORER_H_
#define _CYHAL_TRIGGERS_EXPLORER_H_

/**
 * \addtogroup group_hal_impl_triggers_explorer EXPLORER
 * \ingroup group_hal_impl_triggers
 * \{
 * Trigger connections for explorer
 */

#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */

/** \cond INTERNAL */
/** @brief Name of each input trigger. */
typedef enum
{
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0 = 0, //!< canfd.tr_dbg_dma_req[0]
    _CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1 = 1, //!< canfd.tr_dbg_dma_req[1]
    _CYHAL_TRIGGER_CANFD_TR_FIFO00 = 2, //!< canfd.tr_fifo0[0]
    _CYHAL_TRIGGER_CANFD_TR_FIFO01 = 3, //!< canfd.tr_fifo0[1]
    _CYHAL_TRIGGER_CANFD_TR_FIFO10 = 4, //!< canfd.tr_fifo1[0]
    _CYHAL_TRIGGER_CANFD_TR_FIFO11 = 5, //!< canfd.tr_fifo1[1]
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0 = 6, //!< canfd.tr_tmp_rtp_out[0]
    _CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1 = 7, //!< canfd.tr_tmp_rtp_out[1]
    _CYHAL_TRIGGER_I3C_TR_RX_REQ = 8, //!< i3c.tr_rx_req
    _CYHAL_TRIGGER_I3C_TR_TX_REQ = 9, //!< i3c.tr_tx_req
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 = 10, //!< ioss.peri_tr_io_input_in[0]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 = 11, //!< ioss.peri_tr_io_input_in[1]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 = 12, //!< ioss.peri_tr_io_input_in[2]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 = 13, //!< ioss.peri_tr_io_input_in[3]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 = 14, //!< ioss.peri_tr_io_input_in[4]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 = 15, //!< ioss.peri_tr_io_input_in[5]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 = 16, //!< ioss.peri_tr_io_input_in[6]
    _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 = 17, //!< ioss.peri_tr_io_input_in[7]
    _CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 18, //!< lpcomp.dsi_comp0
    _CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 19, //!< lpcomp.dsi_comp1
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0 = 20, //!< m33syscpuss.cti_tr_out[0]
    _CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1 = 21, //!< m33syscpuss.cti_tr_out[1]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0 = 22, //!< m33syscpuss.dw0_tr_out[0]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1 = 23, //!< m33syscpuss.dw0_tr_out[1]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2 = 24, //!< m33syscpuss.dw0_tr_out[2]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3 = 25, //!< m33syscpuss.dw0_tr_out[3]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4 = 26, //!< m33syscpuss.dw0_tr_out[4]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5 = 27, //!< m33syscpuss.dw0_tr_out[5]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6 = 28, //!< m33syscpuss.dw0_tr_out[6]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7 = 29, //!< m33syscpuss.dw0_tr_out[7]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8 = 30, //!< m33syscpuss.dw0_tr_out[8]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9 = 31, //!< m33syscpuss.dw0_tr_out[9]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10 = 32, //!< m33syscpuss.dw0_tr_out[10]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11 = 33, //!< m33syscpuss.dw0_tr_out[11]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12 = 34, //!< m33syscpuss.dw0_tr_out[12]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13 = 35, //!< m33syscpuss.dw0_tr_out[13]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14 = 36, //!< m33syscpuss.dw0_tr_out[14]
    _CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15 = 37, //!< m33syscpuss.dw0_tr_out[15]
    _CYHAL_TRIGGER_M33SYSCPUSS_ZERO = 38, //!< m33syscpuss.zero
    _CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE = 39, //!< mxnnlite.tr_mxnnlite
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0 = 40, //!< pass.tr_lppass_out[0]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1 = 41, //!< pass.tr_lppass_out[1]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2 = 42, //!< pass.tr_lppass_out[2]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3 = 43, //!< pass.tr_lppass_out[3]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4 = 44, //!< pass.tr_lppass_out[4]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5 = 45, //!< pass.tr_lppass_out[5]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6 = 46, //!< pass.tr_lppass_out[6]
    _CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7 = 47, //!< pass.tr_lppass_out[7]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ0 = 48, //!< pdm.tr_rx_req[0]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ1 = 49, //!< pdm.tr_rx_req[1]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ2 = 50, //!< pdm.tr_rx_req[2]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ3 = 51, //!< pdm.tr_rx_req[3]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ4 = 52, //!< pdm.tr_rx_req[4]
    _CYHAL_TRIGGER_PDM_TR_RX_REQ5 = 53, //!< pdm.tr_rx_req[5]
    _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 54, //!< scb[0].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 55, //!< scb[1].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 56, //!< scb[2].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 57, //!< scb[3].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 58, //!< scb[4].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 59, //!< scb[5].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 60, //!< scb[6].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 61, //!< scb[7].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 62, //!< scb[8].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 63, //!< scb[9].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 64, //!< scb[10].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = 65, //!< scb[11].tr_i2c_scl_filtered
    _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 66, //!< scb[0].tr_rx_req
    _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 67, //!< scb[1].tr_rx_req
    _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 68, //!< scb[2].tr_rx_req
    _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 69, //!< scb[3].tr_rx_req
    _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 70, //!< scb[4].tr_rx_req
    _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 71, //!< scb[5].tr_rx_req
    _CYHAL_TRIGGER_SCB6_TR_RX_REQ = 72, //!< scb[6].tr_rx_req
    _CYHAL_TRIGGER_SCB7_TR_RX_REQ = 73, //!< scb[7].tr_rx_req
    _CYHAL_TRIGGER_SCB8_TR_RX_REQ = 74, //!< scb[8].tr_rx_req
    _CYHAL_TRIGGER_SCB9_TR_RX_REQ = 75, //!< scb[9].tr_rx_req
    _CYHAL_TRIGGER_SCB10_TR_RX_REQ = 76, //!< scb[10].tr_rx_req
    _CYHAL_TRIGGER_SCB11_TR_RX_REQ = 77, //!< scb[11].tr_rx_req
    _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 78, //!< scb[0].tr_tx_req
    _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 79, //!< scb[1].tr_tx_req
    _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 80, //!< scb[2].tr_tx_req
    _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 81, //!< scb[3].tr_tx_req
    _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 82, //!< scb[4].tr_tx_req
    _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 83, //!< scb[5].tr_tx_req
    _CYHAL_TRIGGER_SCB6_TR_TX_REQ = 84, //!< scb[6].tr_tx_req
    _CYHAL_TRIGGER_SCB7_TR_TX_REQ = 85, //!< scb[7].tr_tx_req
    _CYHAL_TRIGGER_SCB8_TR_TX_REQ = 86, //!< scb[8].tr_tx_req
    _CYHAL_TRIGGER_SCB9_TR_TX_REQ = 87, //!< scb[9].tr_tx_req
    _CYHAL_TRIGGER_SCB10_TR_TX_REQ = 88, //!< scb[10].tr_tx_req
    _CYHAL_TRIGGER_SCB11_TR_TX_REQ = 89, //!< scb[11].tr_tx_req
    _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 90, //!< tcpwm[0].tr_out0[0]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 91, //!< tcpwm[0].tr_out0[1]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 92, //!< tcpwm[0].tr_out0[2]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 93, //!< tcpwm[0].tr_out0[3]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT04 = 94, //!< tcpwm[0].tr_out0[4]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT05 = 95, //!< tcpwm[0].tr_out0[5]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT06 = 96, //!< tcpwm[0].tr_out0[6]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT07 = 97, //!< tcpwm[0].tr_out0[7]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 98, //!< tcpwm[0].tr_out0[256]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 99, //!< tcpwm[0].tr_out0[257]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 100, //!< tcpwm[0].tr_out0[258]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 101, //!< tcpwm[0].tr_out0[259]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 102, //!< tcpwm[0].tr_out0[260]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 103, //!< tcpwm[0].tr_out0[261]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 104, //!< tcpwm[0].tr_out0[262]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 105, //!< tcpwm[0].tr_out0[263]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0264 = 106, //!< tcpwm[0].tr_out0[264]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0265 = 107, //!< tcpwm[0].tr_out0[265]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0266 = 108, //!< tcpwm[0].tr_out0[266]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0267 = 109, //!< tcpwm[0].tr_out0[267]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0268 = 110, //!< tcpwm[0].tr_out0[268]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0269 = 111, //!< tcpwm[0].tr_out0[269]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0270 = 112, //!< tcpwm[0].tr_out0[270]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0271 = 113, //!< tcpwm[0].tr_out0[271]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0272 = 114, //!< tcpwm[0].tr_out0[272]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0273 = 115, //!< tcpwm[0].tr_out0[273]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0274 = 116, //!< tcpwm[0].tr_out0[274]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0275 = 117, //!< tcpwm[0].tr_out0[275]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0276 = 118, //!< tcpwm[0].tr_out0[276]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0277 = 119, //!< tcpwm[0].tr_out0[277]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0278 = 120, //!< tcpwm[0].tr_out0[278]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT0279 = 121, //!< tcpwm[0].tr_out0[279]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 122, //!< tcpwm[0].tr_out1[0]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 123, //!< tcpwm[0].tr_out1[1]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 124, //!< tcpwm[0].tr_out1[2]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 125, //!< tcpwm[0].tr_out1[3]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT14 = 126, //!< tcpwm[0].tr_out1[4]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT15 = 127, //!< tcpwm[0].tr_out1[5]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT16 = 128, //!< tcpwm[0].tr_out1[6]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT17 = 129, //!< tcpwm[0].tr_out1[7]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 130, //!< tcpwm[0].tr_out1[256]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 131, //!< tcpwm[0].tr_out1[257]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 132, //!< tcpwm[0].tr_out1[258]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 133, //!< tcpwm[0].tr_out1[259]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 134, //!< tcpwm[0].tr_out1[260]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 135, //!< tcpwm[0].tr_out1[261]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 136, //!< tcpwm[0].tr_out1[262]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 137, //!< tcpwm[0].tr_out1[263]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1264 = 138, //!< tcpwm[0].tr_out1[264]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1265 = 139, //!< tcpwm[0].tr_out1[265]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1266 = 140, //!< tcpwm[0].tr_out1[266]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1267 = 141, //!< tcpwm[0].tr_out1[267]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1268 = 142, //!< tcpwm[0].tr_out1[268]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1269 = 143, //!< tcpwm[0].tr_out1[269]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1270 = 144, //!< tcpwm[0].tr_out1[270]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1271 = 145, //!< tcpwm[0].tr_out1[271]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1272 = 146, //!< tcpwm[0].tr_out1[272]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1273 = 147, //!< tcpwm[0].tr_out1[273]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1274 = 148, //!< tcpwm[0].tr_out1[274]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1275 = 149, //!< tcpwm[0].tr_out1[275]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1276 = 150, //!< tcpwm[0].tr_out1[276]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1277 = 151, //!< tcpwm[0].tr_out1[277]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1278 = 152, //!< tcpwm[0].tr_out1[278]
    _CYHAL_TRIGGER_TCPWM0_TR_OUT1279 = 153, //!< tcpwm[0].tr_out1[279]
    _CYHAL_TRIGGER_TDM_TR_RX_REQ0 = 154, //!< tdm.tr_rx_req[0]
    _CYHAL_TRIGGER_TDM_TR_RX_REQ1 = 155, //!< tdm.tr_rx_req[1]
    _CYHAL_TRIGGER_TDM_TR_TX_REQ0 = 156, //!< tdm.tr_tx_req[0]
    _CYHAL_TRIGGER_TDM_TR_TX_REQ1 = 157, //!< tdm.tr_tx_req[1]
} _cyhal_trigger_source_explorer_t;

/** Typedef for internal device family specific trigger source to generic trigger source */
typedef _cyhal_trigger_source_explorer_t cyhal_internal_source_t;

/** @brief Get a public source signal type (cyhal_trigger_source_explorer_t) given an internal source signal and signal type */
#define _CYHAL_TRIGGER_CREATE_SOURCE(src, type)    ((src) << 1 | (type))
/** @brief Get an internal source signal (_cyhal_trigger_source_explorer_t) given a public source signal. */
#define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src)      ((cyhal_internal_source_t)((src) >> 1))
/** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */
#define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src)        ((cyhal_signal_type_t)((src) & 1))
/** \endcond */

/** @brief Name of each input trigger. */
typedef enum
{
    CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_dbg_dma_req[0]
    CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_dbg_dma_req[1]
    CYHAL_TRIGGER_CANFD_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo0[0]
    CYHAL_TRIGGER_CANFD_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo0[1]
    CYHAL_TRIGGER_CANFD_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo1[0]
    CYHAL_TRIGGER_CANFD_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd.tr_fifo1[1]
    CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd.tr_tmp_rtp_out[0]
    CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd.tr_tmp_rtp_out[1]
    CYHAL_TRIGGER_I3C_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_I3C_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< i3c.tr_rx_req
    CYHAL_TRIGGER_I3C_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_I3C_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< i3c.tr_tx_req
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[0]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[0]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[1]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[1]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[2]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[2]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[3]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[3]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[4]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[4]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[5]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[5]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[6]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[6]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[7]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[7]
    CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp0
    CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp1
    CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.cti_tr_out[0]
    CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.cti_tr_out[1]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[0]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[1]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[2]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[3]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[4]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[5]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[6]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[7]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[8]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[9]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[10]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[11]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[12]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[13]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[14]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.dw0_tr_out[15]
    CYHAL_TRIGGER_M33SYSCPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< m33syscpuss.zero
    CYHAL_TRIGGER_M33SYSCPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_M33SYSCPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< m33syscpuss.zero
    CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_MXNNLITE_TR_MXNNLITE, CYHAL_SIGNAL_TYPE_LEVEL), //!< mxnnlite.tr_mxnnlite
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[0]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[0]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[1]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[1]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[2]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[2]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[3]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[3]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[4]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[4]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[5]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[5]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[6]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[6]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_lppass_out[7]
    CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_lppass_out[7]
    CYHAL_TRIGGER_PDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[0]
    CYHAL_TRIGGER_PDM_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[1]
    CYHAL_TRIGGER_PDM_TR_RX_REQ2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[2]
    CYHAL_TRIGGER_PDM_TR_RX_REQ3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[3]
    CYHAL_TRIGGER_PDM_TR_RX_REQ4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[4]
    CYHAL_TRIGGER_PDM_TR_RX_REQ5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PDM_TR_RX_REQ5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pdm.tr_rx_req[5]
    CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_i2c_scl_filtered
    CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req
    CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req
    CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req
    CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req
    CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req
    CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req
    CYHAL_TRIGGER_SCB6_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_rx_req
    CYHAL_TRIGGER_SCB7_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_rx_req
    CYHAL_TRIGGER_SCB8_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_rx_req
    CYHAL_TRIGGER_SCB9_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_rx_req
    CYHAL_TRIGGER_SCB10_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_rx_req
    CYHAL_TRIGGER_SCB11_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_rx_req
    CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req
    CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req
    CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req
    CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req
    CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req
    CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req
    CYHAL_TRIGGER_SCB6_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB6_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[6].tr_tx_req
    CYHAL_TRIGGER_SCB7_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB7_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[7].tr_tx_req
    CYHAL_TRIGGER_SCB8_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB8_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[8].tr_tx_req
    CYHAL_TRIGGER_SCB9_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB9_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[9].tr_tx_req
    CYHAL_TRIGGER_SCB10_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB10_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[10].tr_tx_req
    CYHAL_TRIGGER_SCB11_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB11_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[11].tr_tx_req
    CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0]
    CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0]
    CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1]
    CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1]
    CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2]
    CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2]
    CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3]
    CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3]
    CYHAL_TRIGGER_TCPWM0_TR_OUT04_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[4]
    CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT04, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[4]
    CYHAL_TRIGGER_TCPWM0_TR_OUT05_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[5]
    CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT05, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[5]
    CYHAL_TRIGGER_TCPWM0_TR_OUT06_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[6]
    CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT06, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[6]
    CYHAL_TRIGGER_TCPWM0_TR_OUT07_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[7]
    CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT07, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[7]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[264]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[264]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[265]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[265]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[266]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[266]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[267]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[267]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0268_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0268, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[268]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0268_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0268, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[268]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0269_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0269, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[269]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0269_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0269, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[269]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0270_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0270, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[270]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0270_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0270, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[270]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0271_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0271, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[271]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0271_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0271, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[271]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0272_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0272, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[272]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0272_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0272, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[272]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0273_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0273, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[273]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0273_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0273, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[273]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0274_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0274, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[274]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0274_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0274, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[274]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0275_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0275, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[275]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0275_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0275, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[275]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0276_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0276, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[276]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0276_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0276, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[276]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0277_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0277, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[277]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0277_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0277, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[277]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0278_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0278, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[278]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0278_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0278, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[278]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0279_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0279, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[279]
    CYHAL_TRIGGER_TCPWM0_TR_OUT0279_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0279, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[279]
    CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0]
    CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0]
    CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1]
    CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1]
    CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2]
    CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2]
    CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3]
    CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3]
    CYHAL_TRIGGER_TCPWM0_TR_OUT14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[4]
    CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT14, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[4]
    CYHAL_TRIGGER_TCPWM0_TR_OUT15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[5]
    CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT15, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[5]
    CYHAL_TRIGGER_TCPWM0_TR_OUT16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[6]
    CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT16, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[6]
    CYHAL_TRIGGER_TCPWM0_TR_OUT17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[7]
    CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT17, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[7]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1264_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[264]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1264, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[264]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1265_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[265]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1265, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[265]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1266_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[266]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1266, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[266]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1267_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[267]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1267, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[267]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1268_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1268, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[268]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1268_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1268, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[268]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1269_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1269, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[269]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1269_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1269, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[269]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1270_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1270, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[270]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1270_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1270, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[270]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1271_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1271, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[271]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1271_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1271, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[271]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1272_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1272, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[272]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1272_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1272, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[272]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1273_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1273, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[273]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1273_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1273, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[273]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1274_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1274, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[274]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1274_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1274, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[274]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1275_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1275, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[275]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1275_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1275, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[275]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1276_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1276, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[276]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1276_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1276, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[276]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1277_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1277, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[277]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1277_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1277, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[277]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1278_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1278, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[278]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1278_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1278, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[278]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1279_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1279, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[279]
    CYHAL_TRIGGER_TCPWM0_TR_OUT1279_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1279, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[279]
    CYHAL_TRIGGER_TDM_TR_RX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_RX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_rx_req[0]
    CYHAL_TRIGGER_TDM_TR_RX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_RX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_rx_req[1]
    CYHAL_TRIGGER_TDM_TR_TX_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_TX_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_tx_req[0]
    CYHAL_TRIGGER_TDM_TR_TX_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TDM_TR_TX_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tdm.tr_tx_req[1]
} cyhal_trigger_source_explorer_t;

/** Typedef from device family specific trigger source to generic trigger source */
typedef cyhal_trigger_source_explorer_t cyhal_source_t;

/** Deprecated defines for signals that can be either level or edge. */
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_M33SYSCPUSS_ZERO (CYHAL_TRIGGER_M33SYSCPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7 (CYHAL_TRIGGER_PASS_TR_LPPASS_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT04 (CYHAL_TRIGGER_TCPWM0_TR_OUT04_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT05 (CYHAL_TRIGGER_TCPWM0_TR_OUT05_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT06 (CYHAL_TRIGGER_TCPWM0_TR_OUT06_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT07 (CYHAL_TRIGGER_TCPWM0_TR_OUT07_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0264 (CYHAL_TRIGGER_TCPWM0_TR_OUT0264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0265 (CYHAL_TRIGGER_TCPWM0_TR_OUT0265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0266 (CYHAL_TRIGGER_TCPWM0_TR_OUT0266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0267 (CYHAL_TRIGGER_TCPWM0_TR_OUT0267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0268 (CYHAL_TRIGGER_TCPWM0_TR_OUT0268_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0269 (CYHAL_TRIGGER_TCPWM0_TR_OUT0269_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0270 (CYHAL_TRIGGER_TCPWM0_TR_OUT0270_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0271 (CYHAL_TRIGGER_TCPWM0_TR_OUT0271_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0272 (CYHAL_TRIGGER_TCPWM0_TR_OUT0272_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0273 (CYHAL_TRIGGER_TCPWM0_TR_OUT0273_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0274 (CYHAL_TRIGGER_TCPWM0_TR_OUT0274_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0275 (CYHAL_TRIGGER_TCPWM0_TR_OUT0275_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0276 (CYHAL_TRIGGER_TCPWM0_TR_OUT0276_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0277 (CYHAL_TRIGGER_TCPWM0_TR_OUT0277_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0278 (CYHAL_TRIGGER_TCPWM0_TR_OUT0278_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT0279 (CYHAL_TRIGGER_TCPWM0_TR_OUT0279_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT14 (CYHAL_TRIGGER_TCPWM0_TR_OUT14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT15 (CYHAL_TRIGGER_TCPWM0_TR_OUT15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT16 (CYHAL_TRIGGER_TCPWM0_TR_OUT16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT17 (CYHAL_TRIGGER_TCPWM0_TR_OUT17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1264 (CYHAL_TRIGGER_TCPWM0_TR_OUT1264_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1265 (CYHAL_TRIGGER_TCPWM0_TR_OUT1265_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1266 (CYHAL_TRIGGER_TCPWM0_TR_OUT1266_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1267 (CYHAL_TRIGGER_TCPWM0_TR_OUT1267_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1268 (CYHAL_TRIGGER_TCPWM0_TR_OUT1268_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1269 (CYHAL_TRIGGER_TCPWM0_TR_OUT1269_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1270 (CYHAL_TRIGGER_TCPWM0_TR_OUT1270_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1271 (CYHAL_TRIGGER_TCPWM0_TR_OUT1271_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1272 (CYHAL_TRIGGER_TCPWM0_TR_OUT1272_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1273 (CYHAL_TRIGGER_TCPWM0_TR_OUT1273_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1274 (CYHAL_TRIGGER_TCPWM0_TR_OUT1274_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1275 (CYHAL_TRIGGER_TCPWM0_TR_OUT1275_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1276 (CYHAL_TRIGGER_TCPWM0_TR_OUT1276_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1277 (CYHAL_TRIGGER_TCPWM0_TR_OUT1277_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1278 (CYHAL_TRIGGER_TCPWM0_TR_OUT1278_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.
#define CYHAL_TRIGGER_TCPWM0_TR_OUT1279 (CYHAL_TRIGGER_TCPWM0_TR_OUT1279_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version.

/** @brief Name of each output trigger. */
typedef enum
{
    CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK0 = 0, //!< TCPWM0_20_31 Trigger multiplexer - canfd.tr_dbg_dma_ack[0]
    CYHAL_TRIGGER_CANFD_TR_DBG_DMA_ACK1 = 1, //!< TCPWM0_20_31 Trigger multiplexer - canfd.tr_dbg_dma_ack[1]
    CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN0 = 2, //!< CAN TT Sync - canfd.tr_evt_swt_in[0]
    CYHAL_TRIGGER_CANFD_TR_EVT_SWT_IN1 = 3, //!< CAN TT Sync - canfd.tr_evt_swt_in[1]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 = 4, //!< Debug Reduction #1 - ioss.peri_tr_io_output_out[0]
    CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 = 5, //!< Debug Reduction #1 - ioss.peri_tr_io_output_out[1]
    CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - m33syscpuss.cti_tr_in[0]
    CYHAL_TRIGGER_M33SYSCPUSS_CTI_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - m33syscpuss.cti_tr_in[1]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN0 = 8, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[0]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN1 = 9, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[1]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN2 = 10, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[2]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN3 = 11, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[3]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN4 = 12, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[4]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN5 = 13, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[5]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN6 = 14, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[6]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN7 = 15, //!< P-DMA0 trigger multiplexer - m33syscpuss.dw0_tr_in[7]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN8 = 16, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[8]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN9 = 17, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[9]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN10 = 18, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[10]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN11 = 19, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[11]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN12 = 20, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[12]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN13 = 21, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[13]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN14 = 22, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[14]
    CYHAL_TRIGGER_M33SYSCPUSS_DW0_TR_IN15 = 23, //!< SCB DW0 Triggers - m33syscpuss.dw0_tr_in[15]
    CYHAL_TRIGGER_PASS_TR_LPPASS_IN0 = 24, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[0]
    CYHAL_TRIGGER_PASS_TR_LPPASS_IN1 = 25, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[1]
    CYHAL_TRIGGER_PASS_TR_LPPASS_IN2 = 26, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[2]
    CYHAL_TRIGGER_PASS_TR_LPPASS_IN3 = 27, //!< P-DMA0 trigger multiplexer - pass.tr_lppass_in[3]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE0 = 28, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[0]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE1 = 29, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[1]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE2 = 30, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[2]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE3 = 31, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[3]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE4 = 32, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[4]
    CYHAL_TRIGGER_PDM_TR_ACTIVATE5 = 33, //!< TCPWM and PDM trigger multiplexer - pdm.tr_activate[5]
    CYHAL_TRIGGER_PDM_TR_DBG_FREEZE = 34, //!< PERI Freeze trigger multiplexer - pdm.tr_dbg_freeze
    CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 35, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
    CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 = 36, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_mcwdt[0]
    CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT1 = 37, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_mcwdt[1]
    CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_WDT = 38, //!< PERI Freeze trigger multiplexer - srss.tr_debug_freeze_wdt
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 39, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[0]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 40, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[1]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 41, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[2]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 42, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[3]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 43, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[4]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 44, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[5]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 45, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[6]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 46, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[7]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 47, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[8]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 48, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[9]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 49, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[10]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 50, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[11]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 51, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[12]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 52, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[13]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 53, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[14]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 54, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[15]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 55, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[16]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 56, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[17]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 57, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[18]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 58, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[19]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 59, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[20]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 60, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[21]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 61, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[22]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 62, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[23]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 63, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[24]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 64, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[25]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 65, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[26]
    CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 = 66, //!< TCPWM0_20_31 Trigger multiplexer - tcpwm[0].tr_all_cnt_in[27]
    CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 67, //!< PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze
    CYHAL_TRIGGER_TDM_TR_DBG_FREEZE = 68, //!< PERI Freeze trigger multiplexer - tdm.tr_dbg_freeze
} cyhal_trigger_dest_explorer_t;

/** Typedef from device family specific trigger dest to generic trigger dest */
typedef cyhal_trigger_dest_explorer_t cyhal_dest_t;

/** \cond INTERNAL */
/** Table of number of inputs to each mux. */
extern const uint16_t cyhal_sources_per_mux[7];

/** Table indicating whether mux is 1to1. */
extern const bool cyhal_is_mux_1to1[7];

/** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
extern const _cyhal_trigger_source_explorer_t* cyhal_mux_to_sources [7];

/** Maps each cyhal_destination_t to a mux index.
 * If bit 8 of the mux index is set, this denotes that the trigger is a
 * one to one trigger.
 */
extern const uint8_t cyhal_dest_to_mux[69];

/* Maps each cyhal_destination_t to a specific output in its mux */
extern const uint8_t cyhal_mux_dest_index[69];
/** \endcond */

#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_impl_triggers_explorer */
#endif /* _CYHAL_TRIGGERS_EXPLORER_H_ */


/* [] END OF FILE */
